80x86 Specifications Project Map

80x86 CPU Feature Flags Specification Version 1.0 (Preliminary Draft)

Contents

1                Overview
1.1                Older Additions
1.2                Future Additions
2                CPU Feature Flags For Executables
3                CPU Features In Chronological Order
4                Feature Flags By Instruction
5                CPU Features Introduced By Intel
5.1                CLFLUSH - CLFLUSH instruction
5.2                CMOVcc - CMOVcc Group Of Instructions
5.3                CMPXCHG8B - CMPXCHG8B Instruction
5.4                CMPXCHG16B - CMPXCHG16B Instruction
5.5                FCMOVcc - FCMOVcc Group Of Instructions
5.6                FISTTP - FISTTP Instruction
5.7                FPU - Floating Point Instructions
5.8                FPU_PRECISE - Precise Floating Point Instructions
5.9                FXSAVE - FXSAVE and FXRSTOR Instructions
5.10               MEMSSE - SSE Memory Operations Instructions
5.11               MMX - MMX Instructions
5.12               MMXSSE - MMX SSE Instructions
5.13               MMXSSE2 - MMX SSE2 Instructions
5.14               MMXSSSE3 - MMX SSSE3 Instructions
5.15               MOVBE - MOVBE Instruction
5.16               SSE - SSE Instructions
5.17               SSE2 - SSE2 Instructions
5.18               SSE3 - SSE3 Instructions
5.19               SSE41 - SSE4.1 Instructions
5.20               SSE42 - SSE4.2 Instructions
5.21               SSSE3 - SSSE3 Instructions
5.22               SYSENTER32 - 32-bit SYSENTER Instruction
6                CPU Features Introduced By AMD
6.1                3DNOW - 3DNow! Instruction Set
6.2                E3DNOW - Extended 3DNow! Instruction Set
6.3                FEMMS Instruction
6.4                LAHF - 64-bit LAHF and SAHF Instructions
6.5                LZCNT - LZCNT Instruction
6.6                MONITOR - MONITOR and MWAIT Instructions
6.7                PFRSQRTV - PFRSQRTV and PFRCPV Instructions
6.8                POPCNT - POPCNT Instruction
6.9                PREFETCHW - PREFETCH and PREFETCHW Instructions
6.10               SSE4A - SSE4A Instruction Set
6.11               SSEALIGN - Unaligned SSE Load Operations
6.12               SYSCALL32 - 32-bit SYSCALL Instruction
6.13               SYSCALL64 - 64-bit SYSCALL Instruction
6.14               SYSENTER64 - 64-bit SYSENTER Instruction
7                CPU Features Introduced By Centaur (VIA)
7.1                AES128 - ACE Instruction Set
7.2                AES196 - ACE Instruction Set
7.3                AES256 - ACE Instruction Set
7.4                MONTMUL - MONTMUL Instruction
7.5                RNG - XSTORE Instruction
7.6                SHA - XSHA1 And XSHA256 Instructions
8                CPU Features Introduced By Cyrix
8.1                CEMMX - Extended MMX Instruction Set


Tables

Table 2.1      CPU Feature Flags For Executables
Table 3.1      CPU Features In Chronological Order
Table 4.1      Feature Flags By Instruction
Table 5.1      CMOVcc Instructions
Table 5.2      FCMOVcc Instructions
Table 5.3      FPU Instructions
Table 5.4      SSE Memory Operations Instructions
Table 5.5      MMX Instructions
Table 5.6      MMX SSE Instructions
Table 5.7      MMX SSE2 Instructions
Table 5.8      MMX SSSE3 Instructions
Table 5.9      SSE Instructions
Table 5.10     SSE2 Instructions
Table 5.11     SSE3 Instructions
Table 5.12     SSE4.1 Instructions
Table 5.13     SSE4.2 Instructions
Table 5.14     SSSE3 Instructions
Table 6.1      3DNow! Instructions
Table 6.2      Extended 3DNow! Instructions
Table 6.3      SSE4A Instructions
Table 7.1      AES128 Instructions
Table 8.1      Extended MMX Instructions



1   Overview

The 8086 CPU was initially released by Intel in 1976, and is the beginning of a long series of compatible CPUs from many manufacturers. Over time, each CPU manufacturer added new features to the architecture; and due to backward compatibility the majority of these features are still present.

This specification defines a standardised set of feature flags are used to describe a set of CPU features that an executable requires, or that an executable might use, or that are supported by the current CPU/s, and for any other similar purposes.

In addition to defining standardised sets of feature flags, this specification will serve as a historical reference for all 80x86 CPU features, and provide details of each feature and lists that may be used for cross-referencing.


1.1   Older Additions

Certain features were added in CPUs that were released before 1990. Some of these features are obsolete (for example, only present in CPUs that don't meet the operating system's minimum requirements) and therefore are ignored in this specification as they are unusable. Some of these features are included as part of the operating system's minimum requirements, and therefore there is no need to mention these features in this specification (executables can assume these features are present, as the operating system refuses to start if they aren't).


1.2   Future Additions

There are several additional features that have been announced by Intel and/or AMD, that haven't been implemented in any currently available CPU. These features include:

• AES insructions • AVX insructions • CLMUL insructions • CVT16 insructions • FMA3 insructions • FMA4 insructions • XOP insructions

In all cases it is unwise to rely on features that have not been released yet, because the implementation of any feature may change after it has been announced (including after full documentation has been provided) but before it is released. Therefore no future extensions are discussed here.


2   CPU Feature Flags For Executables

Bit/s Name Reference    0    CMPXCHG8B    Section 5.3: CMPXCHG8B - CMPXCHG8B Instruction    1    CMOVcc    Section 5.2: CMOVcc - CMOVcc Group Of Instructions    2    SYSCALL32    Section 6.12: SYSCALL32 - 32-bit SYSCALL Instruction    3    SYSCALL64    Section 6.13: SYSCALL64 - 64-bit SYSCALL Instruction    4    SYSENTER32    Section 5.22: SYSENTER32 - 32-bit SYSENTER Instruction    5    SYSENTER64    Section 6.14: SYSENTER64 - 64-bit SYSENTER Instruction    6    CLFLUSH    Section 5.1: CLFLUSH - CLFLUSH instruction    7    MEMSSE    Section 5.10: MEMSSE - SSE Memory Operations Instructions    8    CMPXCHG16B    Section 5.4: CMPXCHG16B - CMPXCHG16B Instruction    9    LAHF    Section 6.4: LAHF - 64-bit LAHF and SAHF Instructions    10    MONITOR    Section 6.6: MONITOR - MONITOR and MWAIT Instructions    11    LZCNT    Section 6.5: LZCNT - LZCNT Instruction    12    POPCNT    Section 6.8: POPCNT - POPCNT Instruction    13    MOVBE    Section 5.15: MOVBE - MOVBE Instruction    14 to 29    Reserved    30    FPU    Section 5.7: FPU - Floating Point Instructions    31    FPU_PRECISE    Section 5.8: FPU_PRECISE - Precise Floating Point Instructions    32    FCMOVcc    Section 5.5: FCMOVcc - FCMOVcc Group Of Instructions    33    FXSAVE    Section 5.9: FXSAVE - FXSAVE and FXRSTOR Instructions    34    FISTTP    Section 5.6: FISTTP - FISTTP Instruction    35 to 39    Reserved    40    FEMMS    Section 6.3: FEMMS Instruction    41    3DNOW    Section 6.1: 3DNOW - 3DNow! Instruction Set    42    PFRSQRTV    Section 6.7: PFRSQRTV - PFRSQRTV and PFRCPV Instructions    43    PREFETCHW    Section 6.9: PREFETCHW - PREFETCH and PREFETCHW Instructions    44    E3DNOW    Section 6.2: E3DNOW - Extended 3DNow! Instruction Set    45 to 49    Reserved    50    MMX    Section 5.11: MMX - MMX Instructions    51    CEMMX    Section 8.1: CEMMX - Extended MMX Instruction Set    52    MMXSSE    Section 5.12: MMXSSE - MMX SSE Instructions    53    MMXSSE2    Section 5.13: MMXSSE2 - MMX SSE2 Instructions    54    MMXSSSE3    Section 5.14: MMXSSSE3 - MMX SSSE3 Instructions    55 to 63    Reserved    64    SSE    Section 5.16: SSE - SSE Instructions    65    SSE2    Section 5.17: SSE2 - SSE2 Instructions    66    SSE3    Section 5.18: SSE3 - SSE3 Instructions    67    SSSE3    Section 5.21: SSSE3 - SSSE3 Instructions    68    SSE4A    Section 6.10: SSE4A - SSE4A Instruction Set    69    SSEALIGN    Section 6.11: SSEALIGN - Unaligned SSE Load Operations    70    SSE41    Section 5.19: SSE41 - SSE4.1 Instructions    71    SSE42    Section 5.20: SSE42 - SSE4.2 Instructions    72 to 95    Reserved    96    RNG    Section 7.5: RNG - XSTORE Instruction    97    AES128    Section 7.1: AES128 - ACE Instruction Set    98    AES196    Section 7.2: AES196 - ACE Instruction Set    99    AES256    Section 7.3: AES256 - ACE Instruction Set    100 to 103    Reserved    104    MONTMUL    Section 7.4: MONTMUL - MONTMUL Instruction    105    SHA    Section 7.6: SHA - XSHA1 And XSHA256 Instructions    106 to 127    Reserved

Table 2.1 - CPU Feature Flags For Executables

3   CPU Features In Chronological Order

Year Name Reference    1986    FPU    Intel 80387, Section 5.7: FPU - Floating Point Instructions    1993    FPU_PRECISE    Intel Pentium, Section 5.7: FPU - Floating Point Instructions    1993    CMPXCHG8B    Intel Pentium, Section 5.3: CMPXCHG8B - CMPXCHG8B Instruction    1995    CMOVcc    Intel Pentium Pro, Section 5.2: CMOVcc - CMOVcc Group Of Instructions    1995    FCMOVcc    Intel Pentium Pro, Section 5.5: FCMOVcc - FCMOVcc Group Of Instructions    1996    MMX    Intel Pentium MMX, Section 5.11: MMX - MMX Instructions    1996    CEMMX    Cyrix 6x86, Section 8.1: CEMMX - Extended MMX Instruction Set    1997    SYSCALL32    AMD K6, Section 6.12: SYSCALL32 - 32-bit SYSCALL Instruction    1997    SYSENTER32    Intel Pentium II, Section 5.22: SYSENTER32 - 32-bit SYSENTER Instruction    1998    FXSAVE    Intel Pentium II (Deschutes), Section 5.9: FXSAVE - FXSAVE and FXRSTOR Instructions    1998    3DNow!    AMD K6-2, Section 6.1: 3DNOW - 3DNow! Instruction Set    1998    FEMMS    AMD K6-2, Section 6.3: FEMMS Instruction    1998    PREFETCHW    AMD K6-2, Section 6.9: PREFETCHW - PREFETCH and PREFETCHW Instructions    1999    MEMSSE    Intel Pentium III, Section 5.10: MEMSSE - SSE Memory Operations Instructions    1999    MMXSSE    Intel Pentium III, Section 5.12: MMXSSE - MMX SSE Instructions    1999    SSE    Intel Pentium III, Section 5.16: SSE - SSE Instructions    1999    E3DNOW    AMD Athlon, Section 6.2: E3DNOW - Extended 3DNow! Instruction Set    2001    CLFLUSH    Intel Pentium 4, Section 5.1: CLFLUSH - CLFLUSH instruction    2001    MMXSSE2    Intel Pentium 4, Section 5.13: MMXSSE2 - MMX SSE2 Instructions    2001    SSE2    Intel Pentium 4, Section 5.17: SSE2 - SSE2 Instructions    2002    PFRSQRTV    AMD Geode GX, Section 6.7: PFRSQRTV - PFRSQRTV and PFRCPV Instructions    2003    SYSCALL64    AMD Athlon 64, Section 6.13: SYSCALL64 - 64-bit SYSCALL Instruction    2003    SYSENTER64    AMD Athlon 64, Section 6.14: SYSENTER64 - 64-bit SYSENTER Instruction    2003    AES128    Centaur Eden ESP (Nehemiah), Section 7.1: AES128 - ACE Instruction Set    2003    AES196    Centaur Eden ESP (Nehemiah), Section 7.2: AES196 - ACE Instruction Set    2003    AES256    Centaur Eden ESP (Nehemiah), Section 7.3: AES256 - ACE Instruction Set    2003    RNG    Centaur Eden ESP (Nehemiah), Section 7.5: RNG - XSTORE Instruction    2004    FISTTP    Intel Pentium 4 (Prescott), Section 5.6: FISTTP - FISTTP Instruction    2004    SSE3    Intel Pentium 4 (Prescott), Section 5.18: SSE3 - SSE3 Instructions    2004    CMPXCHG16B    Intel Pentium 4 (Revision E0), Section 5.4: CMPXCHG16B - CMPXCHG16B Instruction    2004    LAHF    AMD's Athlon 64 (Revision D0), Section 6.4: LAHF - 64-bit LAHF and SAHF Instructions    2006    MMXSSSE3    Intel Core 2, Section 5.14: MMXSSSE3 - MMX SSSE3 Instructions    2006    SSSE3    Intel Core 2, Section 5.21: SSSE3 - SSSE3 Instructions    2006    MONTMUL    Centaur Eden ESP (Esther), Section 7.4: MONTMUL - MONTMUL Instruction    2006    SHA    Centaur Eden ESP (Esther), Section 7.6: SHA - XSHA1 And XSHA256 Instructions    2007    MONITOR    AMD Opteron (Barcelona), Section 6.6: MONITOR - MONITOR and MWAIT Instructions    2007    LZCNT    AMD Opteron (Barcelona), Section 6.5: LZCNT - LZCNT Instruction    2007    POPCNT    AMD Opteron (Barcelona), Section 6.8: POPCNT - POPCNT Instruction    2007    SSE4A    AMD Opteron (Barcelona), Section 6.10: SSE4A - SSE4A Instruction Set    2007    SSEALIGN    AMD Opteron (Barcelona), Section 6.11: SSEALIGN - Unaligned SSE Load Operations    2008    SSE41    Intel Core 2 (Penryn), Section 5.19: SSE41 - SSE4.1 Instructions    2008    SSE42    Intel Core i7, Section 5.20: SSE42 - SSE4.2 Instructions    2008    MOVBE    Intel Atom, Section 5.15: MOVBE - MOVBE Instruction

Table 3.1 - CPU Features In Chronological Order

4   Feature Flags By Instruction

Instruction Feature Flag/s    AAA    None, not allowed in 64-bit code    AAD    None, not allowed in 64-bit code    AAM    None, not allowed in 64-bit code    AAS    None, not allowed in 64-bit code    ADC    None    ADD    None    ADDPD    SSE2    ADDPS    SSE    ADDSD    SSE2    ADDSS    SSE    ADDSUBPD    SSE3    ADDSUBPS    SSE3    AND    None    ANDNPD    SSE2    ANDNPS    SSE    ANDPD    SSE2    ANDPS    SSE    ARPL    None, unneeded, not allowed in 64-bit code    BLENDPD    SSE41    BLENDPS    SSE41    BLENDVPD    SSE41    BLENDVPS    SSE41    BOUND    None, not allowed in 64-bit code    BSF    None    BSR    None    BSWAP    None, part of OS minimum requirements    BT    None    BTC    None    BTR    None    BTS    None    CALL    None    CBW    None    CDQ    None    CDQE    None    CLC    None    CLD    None    CLFLUSH    CLFLUSH    CMC    None    CMOVA    CMOVcc    CMOVAE    CMOVcc    CMOVB    CMOVcc    CMOVBE    CMOVcc    CMOVC    CMOVcc    CMOVE    CMOVcc    CMOVG    CMOVcc    CMOVGE    CMOVcc    CMOVL    CMOVcc    CMOVLE    CMOVcc    CMOVNA    CMOVcc    CMOVNAE    CMOVcc    CMOVNB    CMOVcc    CMOVNBE    CMOVcc    CMOVNC    CMOVcc    CMOVNE    CMOVcc    CMOVNG    CMOVcc    CMOVNGE    CMOVcc    CMOVNL    CMOVcc    CMOVNLE    CMOVcc    CMOVNO    CMOVcc    CMOVNP    CMOVcc    CMOVNS    CMOVcc    CMOVNZ    CMOVcc    CMOVO    CMOVcc    CMOVP    CMOVcc    CMOVPE    CMOVcc    CMOVPO    CMOVcc    CMOVS    CMOVcc    CMOVZ    CMOVcc    CMP    None    CMPEQPD    SSE2    CMPEQPS    SSE    CMPEQSD    SSE2    CMPEQSS    SSE    CMPLEPD    SSE2    CMPLEPS    SSE    CMPLESD    SSE2    CMPLESS    SSE    CMPLTPD    SSE2    CMPLTPS    SSE    CMPLTSD    SSE2    CMPLTSS    SSE    CMPNEQPD    SSE2    CMPNEQPS    SSE    CMPNEQSD    SSE2    CMPNEQSS    SSE    CMPNLEPD    SSE2    CMPNLEPS    SSE    CMPNLESD    SSE2    CMPNLESS    SSE    CMPNLTPD    SSE2    CMPNLTPS    SSE    CMPNLTSD    SSE2    CMPNLTSS    SSE    CMPORDPD    SSE2    CMPORDPS    SSE    CMPORDSD    SSE2    CMPORDSS    SSE    CMPUNORDPD    SSE2    CMPUNORDPS    SSE    CMPUNORDSD    SSE2    CMPUNORDSS    SSE    CMPPD    SSE2    CMPPS    SSE    CMPSB    None    CMPSD (with 32-bit operand/s)    None    CMPSD (with SSE operands)    SSE2    CMPSQ    None, 64-bit code only    CMPSW    None    CMPSS    SSE    CMPXCHG    None, part of OS minimum requirements    CMPXCHG16B    CMPXCHG16B    CMPXCHG8B    CMPXCHG8B    COMISD    SSE2    COMISS    SSE    CQO    None, 64-bit code only    CRC32    SSE42    CVTDQ2PD    SSE2    CVTDQ2PS    SSE2    CVTPD2DQ    SSE2    CVTPD2PI    SSE2    CVTPD2PS    SSE2    CVTPI2PD    SSE2    CVTPI2PS    SSE    CVTPS2DQ    SSE2    CVTPS2PD    SSE2    CVTPS2PI    SSE    CVTSD2SI    SSE2    CVTSD2SS    SSE2    CVTSI2SD    SSE2    CVTSI2SS    SSE    CVTSS2SD    SSE2    CVTSS2SI    SSE    CVTTPD2DQ    SSE2    CVTTPD2PI    SSE2    CVTTPS2DQ    SSE2    CVTTPS2PI    SSE    CVTTSD2SI    SSE2    CVTTSS2SI    SSE    CWD    None    CWDE    None    CWDE    None    DAA    None, not allowed in 64-bit code    DAS    None, not allowed in 64-bit code    DEC    None    DIV    None    DIVPD    SSE2    DIVPS    SSE    DIVSD    SSE2    DIVSS    SSE    DPPD    SSE41    DPPS    SSE41    EMMS    MMX    ENTER    None    EXTRACTPS    SSE41    EXTRQ    SSE4A    F2XM1    FPU, FPU_PRECISE    FABS    FPU, FPU_PRECISE    FADD    FPU, FPU_PRECISE    FADDP    FPU, FPU_PRECISE    FBLD    FPU, FPU_PRECISE    FBSTP    FPU, FPU_PRECISE    FCHS    FPU, FPU_PRECISE    FCLEX    FPU, FPU_PRECISE    FCMOVB    FCMOVcc    FCMOVE    FCMOVcc    FCMOVBE    FCMOVcc    FCMOVU    FCMOVcc    FCMOVNB    FCMOVcc    FCMOVNE    FCMOVcc    FCMOVNBE    FCMOVcc    FCMOVNU    FCMOVcc    FCOM    FPU, FPU_PRECISE    FCOMI    FCMOVcc    FCOMIP    FCMOVcc    FCOMP    FPU, FPU_PRECISE    FCOMPP    FPU, FPU_PRECISE    FCOS    FPU, FPU_PRECISE    FDECSTP    FPU, FPU_PRECISE    FDIV    FPU, FPU_PRECISE    FDIVP    FPU, FPU_PRECISE    FDIVR    FPU, FPU_PRECISE    FDIVRP    FPU, FPU_PRECISE    FEMMS    FEMMS    FFREE    FPU, FPU_PRECISE    FIADD    FPU, FPU_PRECISE    FICOM    FPU, FPU_PRECISE    FICOMP    FPU, FPU_PRECISE    FIDIV    FPU, FPU_PRECISE    FIDIVR    FPU, FPU_PRECISE    FILD    FPU, FPU_PRECISE    FIMUL    FPU, FPU_PRECISE    FINCSTP    FPU, FPU_PRECISE    FINIT    FPU, FPU_PRECISE    FIST    FPU, FPU_PRECISE    FISTP    FPU, FPU_PRECISE    FISUB    FPU, FPU_PRECISE    FISUBR    FPU, FPU_PRECISE    FLD    FPU, FPU_PRECISE    FLD1    FPU, FPU_PRECISE    FLDCW    FPU, FPU_PRECISE    FLDENV    FPU, FPU_PRECISE    FLDL2E    FPU, FPU_PRECISE    FLDL2T    FPU, FPU_PRECISE    FLDLG2    FPU, FPU_PRECISE    FLDLN2    FPU, FPU_PRECISE    FLDPI    FPU, FPU_PRECISE    FLDZ    FPU, FPU_PRECISE    FMUL    FPU, FPU_PRECISE    FMULP    FPU, FPU_PRECISE    FNCLEX    FPU, FPU_PRECISE    FNINIT    FPU, FPU_PRECISE    FNOP    FPU, FPU_PRECISE    FNSAVE    FPU, FPU_PRECISE    FNSTCW    FPU, FPU_PRECISE    FNSTENV    FPU, FPU_PRECISE    FNSTSW    FPU, FPU_PRECISE    FPATAN    FPU, FPU_PRECISE    FPREM    FPU, FPU_PRECISE    FPREM1    FPU, FPU_PRECISE    FPTAN    FPU, FPU_PRECISE    FRNDINT    FPU, FPU_PRECISE    FRSTOR    FPU, FPU_PRECISE    FSAVE    FPU, FPU_PRECISE    FSCALE    FPU, FPU_PRECISE    FSIN    FPU, FPU_PRECISE    FSINCOS    FPU, FPU_PRECISE    FSQRT    FPU, FPU_PRECISE    FST    FPU, FPU_PRECISE    FSTCW    FPU, FPU_PRECISE    FSTENV    FPU, FPU_PRECISE    FSTP    FPU, FPU_PRECISE    FSTSW    FPU, FPU_PRECISE    FSUB    FPU, FPU_PRECISE    FSUBP    FPU, FPU_PRECISE    FSUBR    FPU, FPU_PRECISE    FSUBRP    FPU, FPU_PRECISE    FTST    FPU, FPU_PRECISE    FUCOM    FPU, FPU_PRECISE    FUCOMI    FCMOVcc    FUCOMIP    FCMOVcc    FUCOMP    FPU, FPU_PRECISE    FUCOMPP    FPU, FPU_PRECISE    FWAIT    FPU, FPU_PRECISE    FXAM    FPU, FPU_PRECISE    FXCH    FPU, FPU_PRECISE    FXTRACT    FPU, FPU_PRECISE    FXSAVE    FXSAVE    FXRSTOR    FXSAVE    FYL2X    FPU, FPU_PRECISE    FYL2XP1    FPU, FPU_PRECISE    HADDPD    SSE3    HADDPS    SSE3    HSUBPD    SSE3    HSUBPS    SSE3    IDIV    None    IMUL    None    INC    None    INSERTPS    SSE41    INSERTQ    SSE4A    INT    None, only usable for kernel API    INT3    None, only useful for debugging    INTO    None    IRET    None, unneeded    IRETD    None, unneeded    IRETQ    None, unneeded, 64-bit code only    IRETW    None, unneeded    JA    None    JAE    None    JB    None    JBE    None    JC    None    JCXZ    None    JE    None    JECXZ    None    JG    None    JGE    None    JL    None    JLE    None    JMP    None    JNA    None    JNAE    None    JNB    None    JNBE    None    JNC    None    JNE    None    JNG    None    JNGE    None    JNL    None    JNLE    None    JNO    None    JNP    None    JNS    None    JNZ    None    JO    None    JP    None    JPE    None    JPO    None    JRCXZ    None, 64-bit code only    JS    None    JZ    None    LAHF (32-bit code)    None, not allowed in 64-bit code    LAHF (64-bit code)    LAHF    LDDQU    SSE3    LDMXCSR    SSE    LDS    None, unneeded    LEA    None    LEAVE    None    LES    None, unneeded    LDS    None, unneeded    LFENCE    SSE2    LFS    None, unneeded    LGS    None, unneeded    LODSB    None    LODSD    None    LODSQ    None, 64-bit code only    LODSW    None    LOOP    None    LOOPE    None    LOOPNE    None    LOOPNZ    None    LOOPZ    None    LSS    None, unneeded    LZCNT    LZCNT    MASKMOVDQU    SSE2    MASKMOVQ    MMXSSE    MAXPD    SSE2    MAXPS    SSE    MAXSD    SSE2    MAXSS    SSE    MFENCE    SSE2    MINPD    SSE2    MINPS    SSE    MINSD    SSE2    MINSS    SSE    MONITOR    MONITOR    MOV    None    MOVAPD    SSE2    MOVAPS    SSE    MOVBE    MOVBE    MOVD (with MMX operand/s)    MMX    MOVD (with SSE operand/s)    SSE2    MOVDDUP    SSE3    MOVDQ2Q    MMXSSE2    MOVDQA    SSE2    MOVDQU    SSE2    MOVHPD    SSE2    MOVHPS    SSE    MOVLHPS    SSE    MOVLPD    SSE2    MOVLPS    SSE    MOVHLPS    SSE    MOVMSKPD    SSE2    MOVMSKPS    SSE    MOVNTDQ    SSE2    MOVNTDQA    SSE41    MOVNTI    SSE2    MOVNTPD    SSE2    MOVNTPS    SSE    MOVNTQ    MMXSSE    MOVNTSD    SSE4A    MOVNTSS    SSE4A    MOVQ (with MMX operand/s)    MMX    MOVQ (with SSE operand/s)    SSE2    MOVQ2DQ    MMXSSE2    MOVSB    None    MOVSD (with 32-bit operand/s)    None    MOVSD (with SSE operand/s)    SSE2    MOVSHDUP    SSE3    MOVSLDUP    SSE3    MOVSQ    None, 64-bit code only    MOVSS    SSE    MOVSW    None    MOVSX    None    MOVSXD    None, 64-bit code only    MOVUPD    SSE2    MOVUPS    SSE    MOVZX    None    MPSADBW    SSE41    MUL    None    MULPD    SSE2    MULPS    SSE    MULSD    SSE2    MULSS    SSE    MWAIT    MONITOR    NEG    None    NOP    None    NOT    None    OR    None    ORPD    SSE2    ORPS    SSE    PABSB (with MMX operand/s)    MMXSSSE3    PABSB (with SSE operand/s)    SSSE3    PABSW (with MMX operand/s)    MMXSSSE3    PABSW (with SSE operand/s)    SSSE3    PABSD (with MMX operand/s)    MMXSSSE3    PABSD (with SSE operand/s)    SSSE3    PACKSSDW (with MMX operand/s)    MMX    PACKSSDW (with SSE operand/s)    SSE2    PACKSSWB (with MMX operand/s)    MMX    PACKSSWB (with SSE operand/s)    SSE2    PACKSSWD (with MMX operand/s)    MMX    PACKSSWD (with SSE operand/s)    SSE2    PACKUSDW    SSE41    PACKUSWB (with MMX operand/s)    MMX    PACKUSWB (with SSE operand/s)    SSE2    PADDB (with MMX operand/s)    MMX    PADDB (with SSE operand/s)    SSE2    PADDD (with MMX operand/s)    MMX    PADDD (with SSE operand/s)    SSE2    PADDSB (with MMX operand/s)    MMX    PADDSB (with SSE operand/s)    SSE2    PADDSIW    CEMMX    PADDSW (with MMX operand/s)    MMX    PADDSW (with SSE operand/s)    SSE2    PADDUSB (with MMX operand/s)    MMX    PADDUSB (with SSE operand/s)    SSE2    PADDUSW (with MMX operand/s)    MMX    PADDUSW (with SSE operand/s)    SSE2    PADDW (with MMX operand/s)    MMX    PADDW (with SSE operand/s)    SSE2    PADDQ (with MMX operand/s)    MMXSSE2    PADDQ (with SSE operand/s)    SSE2    PALIGNR (with MMX operand/s)    MMXSSSE3    PALIGNR (with SSE operand/s)    SSSE3    PAND (with MMX operand/s)    MMX    PAND (with SSE operand/s)    SSE2    PANDN (with MMX operand/s)    MMX    PANDN (with SSE operand/s)    SSE2    PAUSE    None, part of OS minimum requirements    PAVEB    CEMMX    PAVGB (with MMX operand/s)    MMXSSE    PAVGB (with SSE operand/s)    SSE2    PAVGUSB    3DNOW    PAVGW (with MMX operand/s)    MMXSSE    PAVGW (with SSE operand/s)    SSE2    PBLENDVB    SSE41    PBLENDW    SSE41    PCMPEQB (with MMX operand/s)    MMX    PCMPEQB (with SSE operand/s)    SSE2    PCMPEQD (with MMX operand/s)    MMX    PCMPEQD (with SSE operand/s)    SSE2    PCMPEQQ    SSE41    PCMPEQW (with MMX operand/s)    MMX    PCMPEQW (with SSE operand/s)    SSE2    PCMPESTRI    SSE42    PCMPESTRM    SSE42    PCMPGTB (with MMX operand/s)    MMX    PCMPGTB (with SSE operand/s)    SSE2    PCMPGTD (with MMX operand/s)    MMX    PCMPGTD (with SSE operand/s)    SSE2    PCMPGTW (with MMX operand/s)    MMX    PCMPGTW (with SSE operand/s)    SSE2    PCMPISTRI    SSE42    PCMPISTRM    SSE42    PCMPGTQ    SSE42    PDISTIB    CEMMX    PEXTRB    SSE41    PEXTRD    SSE41    PEXTRW (with MMX operand/s)    MMXSSE    PEXTRW (opcode "0F C5")    SSE2    PEXTRW (opcode "0F 3A 15")    SSE41    PEXTRQ    SSE41    PF2ID    3DNOW    PF2IW    E3DNOW    PFACC    3DNOW    PFADD    3DNOW    PFCMPEQ    3DNOW    PFCMPGE    3DNOW    PFCMPGT    3DNOW    PFMAX    3DNOW    PFMIN    3DNOW    PFMUL    3DNOW    PFNACC    E3DNOW    PFPNACC    E3DNOW    PFRCP    3DNOW    PFRCPIT1    3DNOW    PFRCPIT2    3DNOW    PFRCPV    PFRSQRTV    PFRSQIT1    3DNOW    PFRSQRT    3DNOW    PFRSQRTV    PFRSQRTV    PFSUB    3DNOW    PFSUBR    3DNOW    PHADDD (with MMX operand/s)    MMXSSSE3    PHADDD (with SSE operand/s)    SSSE3    PHADDSW (with MMX operand/s)    MMXSSSE3    PHADDSW (with SSE operand/s)    SSSE3    PHADDW (with MMX operand/s)    MMXSSSE3    PHADDW (with SSE operand/s)    SSSE3    PHMINPOSUW    SSE41    PHSUBD (with MMX operand/s)    MMXSSSE3    PHSUBD (with SSE operand/s)    SSSE3    PHSUBSW (with MMX operand/s)    MMXSSSE3    PHSUBSW (with SSE operand/s)    SSSE3    PHSUBW (with MMX operand/s)    MMXSSSE3    PHSUBW (with SSE operand/s)    SSSE3    PI2FD    3DNOW    PI2FW    E3DNOW    PINSRB    SSE41    PINSRD    SSE41    PINSRW (with MMX operand/s)    MMXSSE    PINSRW (with SSE operand/s)    SSE2    PINSRQ    SSE41    PMACHRIW    CEMMX    PMADDUBSW (with MMX operand/s)    MMXSSSE3    PMADDUBSW (with SSE operand/s)    SSSE3    PMADDWD (with MMX operand/s)    MMX    PMADDWD (with SSE operand/s)    SSE2    PMAGW    CEMMX    PMAXSB    SSE41    PMAXSD    SSE41    PMAXSW    (with MMX operand/s) MMXSSE    PMAXSW (with SSE operand/s)    SSE2    PMAXUB (with MMX operand/s)    MMXSSE    PMAXUB (with SSE operand/s)    SSE2    PMAXUD    SSE41    PMAXUW    SSE41    PMINSB    SSE41    PMINSD    SSE41    PMINSW (with MMX operand/s)    MMXSSE    PMINSW (with SSE operand/s)    SSE2    PMINUB    (with MMX operand/s) MMXSSE    PMINUB (with SSE operand/s)    SSE2    PMINUD    SSE41    PMINUW    SSE41    PMOVMSKB (with MMX operand/s)    MMXSSE    PMOVMSKB (with SSE operand/s)    SSE2    PMOVSXBW    SSE41    PMOVSXBD    SSE41    PMOVSXBQ    SSE41    PMOVSXWD    SSE41    PMOVSXWQ    SSE41    PMOVSXDQ    SSE41    PMOVZXBW    SSE41    PMOVZXBD    SSE41    PMOVZXBQ    SSE41    PMOVZXWD    SSE41    PMOVZXWQ    SSE41    PMOVZXDQ    SSE41    PMULDQ    SSE41    PMULHRIW    CEMMX    PMULHRSW (with MMX operand/s)    MMXSSSE3    PMULHRSW (with SSE operand/s)    SSSE3    PMULHRW (opcode "0x0F 0x0F")    3DNOW    PMULHRW (opcode "0x0F 0x59")    CEMMX    PMULHUW (with MMX operand/s)    MMXSSE    PMULHUW (with SSE operand/s)    SSE2    PMULHW (with MMX operand/s)    MMX    PMULHW (with SSE operand/s)    SSE2    PMULLD    SSE41    PMULLW (with MMX operand/s)    MMX    PMULLW (with SSE operand/s)    SSE2    PMULUDQ (with MMX operand/s)    MMXSSE2    PMULUDQ (with SSE operand/s)    SSE2    PMVGEZB    CEMMX    PMVLZB    CEMMX    PMVNZB    CEMMX    PMVZB    CEMMX    POP    None    POPA    None, not allowed in 64-bit code    POPAD    None, not allowed in 64-bit code    POPAW    None, not allowed in 64-bit code    POPCNT    POPCNT    POPF    None    POPFD    None, not allowed in 64-bit code    POPFQ    None, 64-bit code only    POPFW    None, not allowed in 64-bit code    POR (with MMX operand/s)    MMX    POR (with SSE operand/s)    SSE2    PREFETCH    PREFETCHW    PREFETCH0    MEMSSE    PREFETCH1    MEMSSE    PREFETCH2    MEMSSE    PREFETCHNTA    MEMSSE    PREFETCHW    PREFETCHW    PSADBW (with MMX operand/s)    MMXSSE    PSADBW (with SSE operand/s)    SSE2    PSHUFB (with MMX operand/s)    MMXSSSE3    PSHUFB (with SSE operand/s)    SSSE3    PSHUFD    SSE2    PSHUFHW    SSE2    PSHUFLW    SSE2    PSHUFW    MMXSSE    PSIGNB (with MMX operand/s)    MMXSSSE3    PSIGNB (with SSE operand/s)    SSSE3    PSIGND (with MMX operand/s)    MMXSSSE3    PSIGND (with SSE operand/s)    SSSE3    PSIGNW (with MMX operand/s)    MMXSSSE3    PSIGNW (with SSE operand/s)    SSSE3    PSLLD (with MMX operand/s)    MMX    PSLLD (with SSE operand/s)    SSE2    PSLLDQ    SSE2    PSLLQ (with MMX operand/s)    MMX    PSLLQ (with SSE operand/s)    SSE2    PSLLW (with MMX operand/s)    MMX    PSLLW (with SSE operand/s)    SSE2    PSRAD (with MMX operand/s)    MMX    PSRAD (with SSE operand/s)    SSE2    PSRAW (with MMX operand/s)    MMX    PSRAW (with SSE operand/s)    SSE2    PSRLD (with MMX operand/s)    MMX    PSRLD (with SSE operand/s)    SSE2    PSRLDQ    SSE2    PSRLQ (with MMX operand/s)    MMX    PSRLQ (with SSE operand/s)    SSE2    PSRLW (with MMX operand/s)    MMX    PSRLW (with SSE operand/s)    SSE2    PSUBB (with MMX operand/s)    MMX    PSUBB (with SSE operand/s)    SSE2    PSUBD (with MMX operand/s)    MMX    PSUBD (with SSE operand/s)    SSE2    PSUBQ (with MMX operand/s)    MMXSSE2    PSUBQ (with SSE operand/s)    SSE2    PSUBSB (with MMX operand/s)    MMX    PSUBSB (with SSE operand/s)    SSE2    PSUBSIW    CEMMX    PSUBSW (with MMX operand/s)    MMX    PSUBSW (with SSE operand/s)    SSE2    PSUBUSB (with MMX operand/s)    MMX    PSUBUSB (with SSE operand/s)    SSE2    PSUBUSW (with MMX operand/s)    MMX    PSUBUSW (with SSE operand/s)    SSE2    PSUBW (with MMX operand/s)    MMX    PSUBW (with SSE operand/s)    SSE2    PSWAPD    E3DNOW    PTEST    SSE41    PUNPCKHBW (with MMX operand/s)    MMX    PUNPCKHBW (with SSE operand/s)    SSE2    PUNPCKHDQ (with MMX operand/s)    MMX    PUNPCKHDQ (with SSE operand/s)    SSE2    PUNPCKHQDQ    SSE2    PUNPCKHWD (with MMX operand/s)    MMX    PUNPCKHWD (with SSE operand/s)    SSE2    PUNPCKLBW (with MMX operand/s)    MMX    PUNPCKLBW (with SSE operand/s)    SSE2    PUNPCKLDQ (with MMX operand/s)    MMX    PUNPCKLDQ (with SSE operand/s)    SSE2    PUNPCKLQDQ    SSE2    PUNPCKLWD (with MMX operand/s)    MMX    PUNPCKLWD (with SSE operand/s)    SSE2    PUSH    None    PUSHA    None, not allowed in 64-bit code    PUSHAD    None, not allowed in 64-bit code    PUSHAW    None, not allowed in 64-bit code    PUSHF    None    PUSHFD    None, not allowed in 64-bit code    PUSHFQ    None, 64-bit code only    PUSHFW    None, not allowed in 64-bit code    PXOR (with MMX operand/s)    MMX    PXOR (with SSE operand/s)    SSE2    RCL    None    RCPPS    SSE    RCPSS    SSE    RCR    None    RET    None    RETF    None    RETN    None    ROL    None    ROUNDPD    SSE41    ROUNDPS    SSE41    ROUNDSD    SSE41    ROUNDSS    SSE41    ROR    None    RSQRTPS    SSE    RSQRTSS    SSE    SAHF (32-bit code)    None, not allowed in 64-bit code    SAHF (64-bit code)    SAHF    SAL    None    SALC    None    SAR    None    SBB    None    SCASB    None    SCASD    None    SCASQ    None, 64-bit code only    SCASW    None    SETA    None    SETAE    None    SETB    None    SETBE    None    SETC    None    SETE    None    SETG    None    SETGE    None    SETL    None    SETLE    None    SETNA    None    SETNAE    None    SETNB    None    SETNBE    None    SETNC    None    SETNE    None    SETNG    None    SETNGE    None    SETNL    None    SETNLE    None    SETNO    None    SETNP    None    SETNS    None    SETNZ    None    SETO    None    SETP    None    SETPE    None    SETPO    None    SETS    None    SETZ    None    SFENCE    MEMSSE    SGDT    None, unneeded    SHL    None    SHLD    None    SHR    None    SHRD    None    SHUFPD    SSE2    SHUFPS    SSE    SIDT    None, unneeded    SLDT    None, unneeded    SQRTPD    SSE2    SQRTPS    SSE    SQRTSD    SSE2    SQRTSS    SSE    STC    None    STD    None    STMXCSR    SSE    STOSB    None    STOSD    None    STOSQ    None, 64-bit code only    STOSW    None    STR    None, unneeded    SUB    None    SUBPD    SSE2    SUBPS    SSE    SUBSD    SSE2    SUBSS    SSE    SYSCALL    SYSCALL32, SYSCALL64    SYSENTER    SYSENTER32, SYSENTER64    TEST    None    UCOMISD    SSE2    UCOMISS    SSE    UD2    None, part of OS minimum requirements    UNPCKHPD    SSE2    UNPCKHPS    SSE    UNPCKLPD    SSE2    UNPCKLPS    SSE    VERR    None, unneeded    VERW    None, unneeded    WAIT    FPU, FPU_PRECISE    XADD    None, part of OS minimum requirements    XCHG    None    XCRYPTCBC    AES128,AES196,AES256    XCRYPTCFB    AES128,AES196,AES256    XCRYPTCTR    AES128,AES196,AES256    XCRYPTECB    AES128,AES196,AES256    XCRYPTOFB    AES128,AES196,AES256    XLAT    None    XLATB    None    XOR    None    XORPD    SSE2    XORPS    SSE    XSHA1    SHA    XSHA256    SHA    XSTORE    RNG

Table 4.1 - Feature Flags By Instruction

5   CPU Features Introduced By Intel

5.1   CLFLUSH - CLFLUSH instruction

The CMPXCHG8B instruction was introduced in Intel's Pentium 4 CPU, first released in 2001.


5.2   CMOVcc - CMOVcc Group Of Instructions

The conditional move (CMOVcc) group of instructions were introduced in Intel's Pentium Pro CPU, first released in 1995. Instructions that belong to the CMOVcc group of instructions are listed in Table 5.1: CMOVcc Instructions.

CMOVA CMOVAE CMOVB CMOVBE CMOVC CMOVE CMOVG CMOVGE CMOVL CMOVLE CMOVNA CMOVNAE CMOVNB CMOVNBE CMOVNC CMOVNE CMOVNG CMOVNGE CMOVNL CMOVNLE CMOVNO CMOVNP CMOVNS CMOVNZ CMOVO CMOVP CMOVPE CMOVPO CMOVS CMOVZ

Table 5.1 - CMOVcc Instructions

5.3   CMPXCHG8B - CMPXCHG8B Instruction

The CMPXCHG8B instruction was introduced in Intel's Pentium CPU, first released in 1993.


5.4   CMPXCHG16B - CMPXCHG16B Instruction

The CMPXCHG8B instruction was introduced in Intel's Pentium 4 CPU (Prescott, Revision E0, not earlier versions), first released in 2004.


5.5   FCMOVcc - FCMOVcc Group Of Instructions

The floating point conditional move and comparison group of instructions were introduced in Intel's Pentium Pro CPU, first released in 1995. Instructions that belong to the FCMOVcc group of instructions are listed in Table 5.2: FCMOVcc Instructions.

FCMOVB FCMOVE FCMOVBE FCMOVU FCMOVNB FCMOVNE FCMOVNBE FCMOVNU FCOMI FCOMIP FUCOMI FUCOMIP

Table 5.2 - FCMOVcc Instructions

5.6   FISTTP - FISTTP Instruction

The FISTTP instructions requires both FPU and SSE3. It was introduced as part of SSE3 in Intel's Pentium 4 CPU (Prescott, not earlier versions), first released in 2004. A separate flag is used for this instruction so that it's possible for the operating system to support SSE3 without supporting FPU.


5.7   FPU - Floating Point Instructions

The Floating Point Instructions set was first introduced by Intel as a coprocessor (the 8087), however the first 32-bit version was introduced as the 80387 in 1986. Instructions that belong to the FPU instruction set are listed in Table 5.3: FPU Instructions.

F2XM1 FABS FADD FADDP FBLD FBSTP FCHS FCLEX FCOM FCOMP FCOMPP FCOS FDECSTP FDIV FDIVP FDIVR FDIVRP FFREE FIADD FICOM FICOMP FIDIV FIDIVR FILD FIMUL FINCSTP FINIT FIST FISTP FISUB FISUBR FLD FLD1 FLDCW FLDENV FLDL2E FLDL2T FLDLG2 FLDLN2 FLDPI FLDZ FMUL FMULP FNCLEX FNINIT FNOP FNSAVE FNSTCW FNSTENV FNSTSW FPATAN FPREM FPREM1 FPTAN FRNDINT FRSTOR FSAVE FSCALE FSIN FSINCOS FSQRT FST FSTCW FSTENV FSTP FSTSW FSUB FSUBP FSUBR FSUBRP FTST FUCOM FUCOMP FUCOMPP FWAIT FXAM FXCH FXTRACT FYL2X FYL2XP1 FWAIT WAIT

Table 5.3 - FPU Instructions

5.8   FPU_PRECISE - Precise Floating Point Instructions

Some CPUs support FPU instructions, but have precision problems with some instructions (where the results aren't necessarily as precise as they should be). In this case, the FPU is still suitable for a large number of purposes (e.g. graphics) but may be considered unusable for other purposes (e.g. accountancy, finance). To cope with this difference 2 separate feature flags are defined - one feature flag to indicate that FPU is present or required, and another feature flag to indicate that a precise FPU is present or required.

For the purpose of Chapter 3: CPU Features In Chronological Order, Intel released the FPU_PRECISE feature when they released the original Pentium CPU, which (as far as I know) was the first FPU that had non-precise behaviour (for the original Pentium CPU, the FDIV instruction produces inaccurate results in extremely rare but easily reproduced situations).

The FPU_PRECISE feature flag covers exactly the same instructions as the FPU feature flag (these FPU instruction set are listed in Table 5.3: FPU Instructions).


5.9   FXSAVE - FXSAVE and FXRSTOR Instructions

The FXSAVE and FXRSTOR instructions were introduced in Intel's Pentium II CPU (Deschutes, not earlier versions), first released in 1998.


5.10   MEMSSE - SSE Memory Operations Instructions

These instructions were introduced as part of SSE, but don't require SSE. They were introduced as part of SSE in Intel's Pentium III CPU, first released in 1999. A separate flag is used for these instructions so that it's possible for the operating system to support SSE without supporting these instructions, and so that the operating system can support these instructions without supporting SSE. Also note that some CPUs support these instructions even though they don't support SSE itself (e.g. earlier AMD Athlon CPUs). Instructions that belong to this group of instructions are listed in Table 5.4: SSE Memory Operations Instructions.

PREFETCH0 PREFETCH1 PREFETCH2 PREFETCHNTA SFENCE

Table 5.4 - SSE Memory Operations Instructions

5.11   MMX - MMX Instructions

The MMX instruction set was introduced in Intel's Pentium MMX CPU, first released in 1996. Instructions that belong to the MMX instruction set are listed in Table 5.5: MMX Instructions.

EMMS MOVD (with MMX operand/s) MOVQ (with MMX operand/s) PACKSSDW (with MMX operand/s) PACKSSWB (with MMX operand/s) PACKSSWD (with MMX operand/s) PACKUSWB (with MMX operand/s) PADDB (with MMX operand/s) PADDD (with MMX operand/s) PADDSB (with MMX operand/s) PADDSW (with MMX operand/s) PADDUSB (with MMX operand/s) PADDUSW (with MMX operand/s) PADDW (with MMX operand/s) PAND (with MMX operand/s) PANDN (with MMX operand/s) PCMPEQB (with MMX operand/s) PCMPEQD (with MMX operand/s) PCMPEQW (with MMX operand/s) PCMPGTB (with MMX operand/s) PCMPGTD (with MMX operand/s) PCMPGTW (with MMX operand/s) PMADDWD (with MMX operand/s) PMULHW (with MMX operand/s) PMULLW (with MMX operand/s) POR (with MMX operand/s) PSLLD (with MMX operand/s) PSLLQ (with MMX operand/s) PSLLW (with MMX operand/s) PSRAD (with MMX operand/s) PSRAW (with MMX operand/s) PSRLD (with MMX operand/s) PSRLQ (with MMX operand/s) PSRLW (with MMX operand/s) PSUBB (with MMX operand/s) PSUBD (with MMX operand/s) PSUBSB (with MMX operand/s) PSUBSW (with MMX operand/s) PSUBUSB (with MMX operand/s) PSUBUSW (with MMX operand/s) PSUBW (with MMX operand/s) PUNPCKHBW (with MMX operand/s) PUNPCKHDQ (with MMX operand/s) PUNPCKHWD (with MMX operand/s) PUNPCKLBW (with MMX operand/s) PUNPCKLDQ (with MMX operand/s) PUNPCKLWD (with MMX operand/s) PXOR (with MMX operand/s)

Table 5.5 - MMX Instructions

5.12   MMXSSE - MMX SSE Instructions

These instructions are instructions that require both MMX and SSE. They were introduced as part of SSE in Intel's Pentium III CPU, first released in 1999. A separate flag is used for these instructions so that it's possible for the operating system to support SSE without supporting MMX or to support these instructions without supporting SSE. Also note that some CPU that support MMX also support these instructions even though they don't support SSE itself (e.g. earlier AMD Athlon CPUs). Instructions that belong to this group of instructions are listed in Table 5.6: MMX SSE Instructions.

MASKMOVQ MOVNTQ PAVGB (with MMX operand/s) PAVGW (with MMX operand/s) PEXTRW (with MMX operand/s) PINSRW (with MMX operand/s) PMAXSW (with MMX operand/s) PMAXUB (with MMX operand/s) PMINSW (with MMX operand/s) PMINUB (with MMX operand/s) PMOVMSKB (with MMX operand/s) PMULHUW (with MMX operand/s) PSADBW (with MMX operand/s) PSHUFW

Table 5.6 - MMX SSE Instructions

5.13   MMXSSE2 - MMX SSE2 Instructions

These instructions are instructions that require both MMX and SSE2. They were introduced as part of SSE2 in Intel's Pentium 4 CPU, first released in 2001. A separate flag is used for these instructions so that it's possible for the operating system to support SSE2 without supporting MMX or to support these instructions without supporting SSE2. Instructions that belong to this group of instructions are listed in Table 5.7: MMX SSE2 Instructions.

MOVDQ2Q MOVQ2DQ PADDQ (with MMX operand/s) PSUBQ (with MMX operand/s) PMULUDQ (with MMX operand/s)

Table 5.7 - MMX SSE2 Instructions

5.14   MMXSSSE3 - MMX SSSE3 Instructions

These instructions are instructions that require both MMX and SSSE3. They were introduced as part of SSSE3 in Intel's Core 2 CPU, first released in 2006. A separate flag is used for these instructions so that it's possible for the operating system to support SSSE3 without supporting MMX or to support these instructions without supporting SSSE3. Instructions that belong to this group of instructions are listed in Table 5.8: MMX SSSE3 Instructions.

PABSB (with MMX operand/s) PABSW (with MMX operand/s) PABSD (with MMX operand/s) PALIGNR (with MMX operand/s) PHADDW (with MMX operand/s) PHADDD (with MMX operand/s) PHADDSW (with MMX operand/s) PHSUBW (with MMX operand/s) PHSUBD (with MMX operand/s) PHSUBSW (with MMX operand/s) PMADDUBSW (with MMX operand/s) PMULHRSW (with MMX operand/s) PSHUFB (with MMX operand/s) PSIGNB (with MMX operand/s) PSIGNW (with MMX operand/s) PSIGND (with MMX operand/s)

Table 5.8 - MMX SSSE3 Instructions

5.15   MOVBE - MOVBE Instruction

The MOVEBE instruction was introduced in Intel's Atom CPU, first released in 2008.


5.16   SSE - SSE Instructions

The SSE instruction set was introduced in Intel's Pentium III CPU, first released in 1999. Instructions that belong to the SSE instruction set are listed in Table 5.9: SSE Instructions.

ADDPS ADDSS ANDNPS ANDPS CMPEQPS CMPEQSS CMPLEPS CMPLESS CMPLTPS CMPLTSS CMPNEQPS CMPNEQSS CMPNLEPS CMPNLESS CMPNLTPS CMPNLTSS CMPORDPS CMPORDSS CMPUNORDPS CMPUNORDSS CMPPS CMPSS COMISS CVTPI2PS CVTPS2PI CVTSI2SS CVTSS2SI CVTTPS2PI CVTTSS2SI DIVPS DIVSS LDMXCSR MAXPS MAXSS MINPS MINSS MOVAPS MOVHPS MOVLHPS MOVLPS MOVHLPS MOVMSKPS MOVNTPS MOVSS MOVUPS MULPS MULSS ORPS RCPPS RCPSS RSQRTPS RSQRTSS SHUFPS SQRTPS SQRTSS STMXCSR SUBPS SUBSS UCOMISS UNPCKHPS UNPCKLPS XORPS

Table 5.9 - SSE Instructions

5.17   SSE2 - SSE2 Instructions

The SSE2 instruction set was introduced in Intel's Pentium 4 CPU, first released in 2001. Instructions that belong to the SSE2 instruction set are listed in Table 5.10: SSE2 Instructions.

ADDPD ADDSD ANDNPD ANDPD CMPEQPD CMPEQSD CMPLEPD CMPLESD CMPLTPD CMPLTSD CMPNEQPD CMPNEQSD CMPNLEPD CMPNLESD CMPNLTPD CMPNLTSD CMPORDPD CMPORDSD CMPUNORDPD CMPUNORDSD CMPPD CMPSD (with SSE operands) COMISD CVTDQ2PD CVTDQ2PS CVTPD2DQ CVTPD2PI CVTPD2PS CVTPI2PD CVTPS2DQ CVTPS2PD CVTSD2SI CVTSD2SS CVTSI2SD CVTSS2SD CVTTPD2PI CVTTPD2DQ CVTTPS2DQ CVTTSD2SI DIVPD DIVSD LFENCE MASKMOVDQU MAXPD MAXSD MFENCE MINPD MINSD MOVAPD MOVD (with SSE operand/s) MOVDQA MOVDQU MOVHPD MOVLPD MOVMSKPD MOVNTDQ MOVNTI MOVNTPD MOVQ (with SSE operand/s) MOVSD (with SSE operand/s) MOVUPD MULPD MULSD ORPD PACKSSDW (with SSE operand/s) PACKSSWB (with SSE operand/s) PACKSSWD (with SSE operand/s) PACKUSWB (with SSE operand/s) PADDB (with SSE operand/s) PADDD (with SSE operand/s) PADDSB (with SSE operand/s) PADDSW (with SSE operand/s) PADDUSB (with SSE operand/s) PADDUSW (with SSE operand/s) PADDW (with SSE operand/s) PADDQ (with SSE operand/s) PAND (with SSE operand/s) PANDN (with SSE operand/s) PAVGB (with SSE operand/s) PAVGW (with SSE operand/s) PCMPEQB (with SSE operand/s) PCMPEQD (with SSE operand/s) PCMPEQW (with SSE operand/s) PCMPGTB (with SSE operand/s) PCMPGTD (with SSE operand/s) PCMPGTW (with SSE operand/s) PEXTRW (opcode "0F C5") PINSRW (with SSE operand/s) PMADDWD (with SSE operand/s) PMAXSW (with SSE operand/s) PMAXUB (with SSE operand/s) PMINSW (with SSE operand/s) PMINUB (with SSE operand/s) PMOVMSKB (with SSE operand/s) PMULHUW (with SSE operand/s) PMULHW (with SSE operand/s) PMULLW (with SSE operand/s) PMULUDQ (with SSE operand/s) POR (with SSE operand/s) PSADBW (with SSE operand/s) PSHUFD PSHUFHW PSHUFLW PSLLD (with SSE operand/s) PSLLDQ PSLLQ (with SSE operand/s) PSLLW (with SSE operand/s) PSRAD (with SSE operand/s) PSRAW (with SSE operand/s) PSRLD (with SSE operand/s) PSRLDQ PSRLQ (with SSE operand/s) PSRLW (with SSE operand/s) PSUBB (with SSE operand/s) PSUBD (with SSE operand/s) PSUBQ (with SSE operand/s) PSUBW (with SSE operand/s) PSUBSB (with SSE operand/s) PSUBSW (with SSE operand/s) PSUBUSB (with SSE operand/s) PSUBUSW (with SSE operand/s) PUNPCKHBW (with SSE operand/s) PUNPCKHDQ (with SSE operand/s) PUNPCKHQDQ PUNPCKHWD (with SSE operand/s) PUNPCKLBW (with SSE operand/s) PUNPCKLDQ (with SSE operand/s) PUNPCKLQDQ PUNPCKLWD (with SSE operand/s) PXOR (with SSE operand/s) SHUFPD SQRTPD SQRTSD SUBPD SUBSD UCOMISD UNPCKHPD UNPCKLPD XORPD

Table 5.10 - SSE2 Instructions

5.18   SSE3 - SSE3 Instructions

The SSE3 instruction set was introduced in Intel's Pentium 4 CPU (Prescott, not earlier versions), first released in 2004. Instructions that belong to the SSE3 instruction set are listed in Table 5.11: SSE3 Instructions.

ADDSUBPD ADDSUBPS HADDPD HADDPS HSUBPD HSUBPS LDDQU MOVDDUP MOVSHDUP MOVSLDUP

Table 5.11 - SSE3 Instructions

5.19   SSE41 - SSE4.1 Instructions

The SSE4.1 instruction set was introduced in Intel's Core 2 CPU (Penryn, not earlier versions), first released in 2008. Instructions that belong to the SSE4.1 instruction set are listed in Table 5.12: SSE4.1 Instructions.

BLENDPD BLENDPS BLENDVPD BLENDVPS DPPD DPPS EXTRACTPS INSERTPS MOVNTDQA MPSADBW PACKUSDW PBLENDVB PBLENDW PCMPEQQ PEXTRB PEXTRD PEXTRQ PEXTRW (opcode "0F 3A 15") PHMINPOSUW PINSRB PINSRD PINSRQ PMAXSB PMAXSD PMAXUD PMAXUW PMINSB PMINSD PMINUD PMINUW PMOVSXBW PMOVSXBD PMOVSXBQ PMOVSXWD PMOVSXWQ PMOVSXDQ PMOVZXBW PMOVZXBD PMOVZXBQ PMOVZXWD PMOVZXWQ PMOVZXDQ PMULDQ PMULLD PTEST ROUNDPD ROUNDPS ROUNDSD ROUNDSS

Table 5.12 - SSE4.1 Instructions

5.20   SSE42 - SSE4.2 Instructions

The SSE4.2 instruction set was introduced in Intel's Core i7 CPU, first released in 2008. Instructions that belong to the SSE4.2 instruction set are listed in Table 5.13: SSE4.2 Instructions.

CRC32 PCMPESTRI PCMPESTRM PCMPISTRI PCMPISTRM PCMPGTQ

Table 5.13 - SSE4.2 Instructions

5.21   SSSE3 - SSSE3 Instructions

The SSSE3 instruction set was introduced in Intel's Core 2 CPU, first released in 2006. Instructions that belong to the SSSE3 instruction set are listed in Table 5.14: SSSE3 Instructions.

PABSB (with SSE operand/s) PABSW (with SSE operand/s) PABSD (with SSE operand/s) PALIGNR (with SSE operand/s) PHADDW (with SSE operand/s) PHADDD (with SSE operand/s) PHADDSW (with SSE operand/s) PHSUBW (with SSE operand/s) PHSUBD (with SSE operand/s) PHSUBSW (with SSE operand/s) PMADDUBSW (with SSE operand/s) PMULHRSW (with SSE operand/s) PSHUFB (with SSE operand/s) PSIGNB (with SSE operand/s) PSIGNW (with SSE operand/s) PSIGND (with SSE operand/s)

Table 5.14 - SSSE3 Instructions

5.22   SYSENTER32 - 32-bit SYSENTER Instruction

The SYSENTER instruction was introduced in Intel's Pentium II CPU, first released in 1997.

Due to competition between AMD and Intel, the SYSENTER instruction may be supported in protected mode and not supported in long mode, and therefore a separate feature flag is used for the 32-bit version and the 64-bit version of the same instruction.


6   CPU Features Introduced By AMD

6.1   3DNOW - 3DNow! Instruction Set

The 3DNow! instruction set was introduced in AMD's K6-2 CPU, first released in 1998. Instructions that belong to the 3DNow! instruction set are listed in Table 6.1: 3DNow! Instructions.

FEMMS PAVGUSB PF2ID PFACC PFADD PFCMPEQ PFCMPGE PFCMPGT PFMAX PFMIN PFMUL PMULHRW (opcode "0x0F 0x0F") PFRCP PFRCPIT1 PFRCPIT2 PFRSQIT1 PFRSQRT PFSUB PFSUBR PI2FD

Table 6.1 - 3DNow! Instructions

6.2   E3DNOW - Extended 3DNow! Instruction Set

The Extended 3DNow! instruction set was introduced in AMD's Athlon CPU, first released in 1999. Instructions that belong to the Extended 3DNow! instruction set are listed in Table 6.2: Extended 3DNow! Instructions.

PF2IW PI2FW PFNACC PFPNACC PSWAPD

Table 6.2 - Extended 3DNow! Instructions

6.3   FEMMS Instruction

The 3DNow! instruction set was introduced in AMD's K6-2 CPU, first released in 1998. Some CPUs report support for FEMMS separate to support for 3DNow!, so the operating system also uses separate flags for FEMMS and 3DNow! in case there's ever a reason for it.


6.4   LAHF - 64-bit LAHF and SAHF Instructions

When AMD first introduced long mode 64-bit code was unable to use the LAHF and SAHF instructions (but 16-bit and 32-bit code still could). Support for LAHF and SAHF instructions was added later in AMD's Athlon 64 CPU (Revision D0, not earlier versions), first released in 2004.

Note: In the earliest AMD CPUs that supported LAHF and SAHF there was a CPU bug that caused CPUID to report that these instructions aren't supported, so some sources incorrectly assume that support for LAHF and SAHF in 64-bit code was added in later CPUs, in 2005


6.5   LZCNT - LZCNT Instruction

The LZCNT instruction was introduced in AMD's Opteron CPU (Barcelona, not earlier versions), first released in 2007.


6.6   MONITOR - MONITOR and MWAIT Instructions

The MONITOR and MWAIT instructions were introduced in Intel's Pentium 4 CPU (Prescott, not earlier versions), first released in 2004; however these instructions were only available to kernel code (at CPL=0). Since these instructions were introduced Intel's documentation has mentioned that they may be available to normal executables (at CPL=3), but Intel still hasn't released a CPU that does make these instructions available to normal executables.

AMD was the first (and probably, the only) CPU manufacturer to make the MONITOR and MWAIT instructions available (at CPL=3) to normal executables. They were introduced in AMD's Opteron CPU (Barcelona, not earlier versions), first released in 2007.


6.7   PFRSQRTV - PFRSQRTV and PFRCPV Instructions

The PFRSQRTV and PFRCPV instructions were introduced in AMD's Geode GX CPU, first released in 2002.


6.8   POPCNT - POPCNT Instruction

The POPCNT instruction was introduced in AMD's Opteron CPU (Barcelona, not earlier versions), first released in 2007.


6.9   PREFETCHW - PREFETCH and PREFETCHW Instructions

The PREFETCH and PREFETCHW instructions were introduced as part of 3DNow! in AMD's K6-2 CPU, first released in 1998. Since then AMD introduced a separate CPUID flag to indicate support for PREFETCH and PREFETCHW alone. The only sane reason for AMD to introduce the new CPUID flag is if AMD is planning to drop support for 3DNow! while keeping support for PREFETCH and PREFETCHW.


6.10   SSE4A - SSE4A Instruction Set

The SSE4A instruction set was introduced in AMD's Opteron CPU (Barcelona, not earlier versions), first released in 2007. Instructions that belong to the SSE4A instruction set are listed in Table 6.3: SSE4A Instructions.

EXTRQ INSERTQ MOVNTSD MOVNTSS

Table 6.3 - SSE4A Instructions

6.11   SSEALIGN - Unaligned SSE Load Operations

The "unaligned SSE load operations" feature was introduced in AMD's Opteron CPU (Barcelona, not earlier versions), first released in 2007. This feature relaxes the alignment requirements for some existing SSE Instructions, and doesn't add any new instructions.


6.12   SYSCALL32 - 32-bit SYSCALL Instruction

The SYSCALL instruction was introduced in AMD's K6 CPU, first released in 1997.

Due to competition between AMD and Intel, the SYSCALL instruction may be supported in long mode and not supported in protected mode, and therefore a separate feature flag is used for the 32-bit version and the 64-bit version of the same instruction.


6.13   SYSCALL64 - 64-bit SYSCALL Instruction

The SYSCALL instruction was introduced in AMD's K6 CPU, first released in 1997.

Due to competition between AMD and Intel, the SYSCALL instruction may be supported in long mode and not supported in protected mode, and therefore a separate feature flag is used for the 32-bit version and the 64-bit version of the same instruction.

For the purpose of Chapter 3: CPU Features In Chronological Order, AMD released the SYSCALL64 feature when they released the first CPU to support long mode.


6.14   SYSENTER64 - 64-bit SYSENTER Instruction

The SYSENTER instruction was introduced in Intel's Pentium II CPU, first released in 1997.

Due to competition between AMD and Intel, the SYSENTER instruction may be supported in protected mode and not supported in long mode, and therefore a separate feature flag is used for the 32-bit version and the 64-bit version of the same instruction.

For the purpose of Chapter 3: CPU Features In Chronological Order, AMD released the SYSENTER64 feature when they released the first CPU to support long mode.


7   CPU Features Introduced By Centaur (VIA)

7.1   AES128 - ACE Instruction Set

The ACE instruction set was introduced in Centaur's Eden ESP CPU (Nehemiah, not earlier versions), first released in 2003. The ACE instruction set is split into 3 separate feature flags by the operating system (AES128, AES196 and AES256) because some CPUs that support ACE don't work correctly for some encryption key sizes. The AES128 feature flag indicates that the CPU supports the ACE instruction set and works correctly for 128-bit AES encryption/decryption. Instructions that belong to the ACE instruction set are listed in Table 7.1: AES128 Instructions.

XCRYPTCBC XCRYPTCFB XCRYPTCTR XCRYPTECB XCRYPTOFB

Table 7.1 - AES128 Instructions

7.2   AES196 - ACE Instruction Set

The ACE instruction set was introduced in Centaur's Eden ESP CPU (Nehemiah, not earlier versions), first released in 2003. The ACE instruction set is split into 3 separate feature flags by the operating system (AES128, AES196 and AES256) because some CPUs that support ACE don't work correctly for some encryption key sizes. The AES196 feature flag indicates that the CPU supports the ACE instruction set and works correctly for 196-bit AES encryption/decryption. Instructions that belong to the ACE instruction set are listed in Table 7.1: AES128 Instructions.


7.3   AES256 - ACE Instruction Set

The ACE instruction set was introduced in Centaur's Eden ESP CPU (Nehemiah, not earlier versions), first released in 2003. The ACE instruction set is split into 3 separate feature flags by the operating system (AES128, AES196 and AES256) because some CPUs that support ACE don't work correctly for some encryption key sizes. The AES256 feature flag indicates that the CPU supports the ACE instruction set and works correctly for 256-bit AES encryption/decryption. Instructions that belong to the ACE instruction set are listed in Table 7.1: AES128 Instructions.


7.4   MONTMUL - MONTMUL Instruction

The MONTMUL instruction was introduced in Centaur's Eden ESP CPU (Esther, not earlier versions), first released in 2006.


7.5   RNG - XSTORE Instruction

The XSTORE instruction was introduced in Centaur's Eden ESP CPU (Nehemiah, not earlier versions), first released in 2003.


7.6   SHA - XSHA1 And XSHA256 Instructions

The XSHA1 and XSHA256 instructions were introduced in Centaur's Eden ESP CPU (Esther, not earlier versions), first released in 2006.


8   CPU Features Introduced By Cyrix

8.1   CEMMX - Extended MMX Instruction Set

The Extended MMX instruction set was introduced in Cyrix's 6x86 CPU, first released in 1996. Instructions that belong to the Extended MMX instruction set are listed in Table 8.1: Extended MMX Instructions.

PADDSIW PAVEB PDISTIB PMACHRIW PMAGW PMULHRIW PMULHRW (opcode "0x0F 0x59") PMVGEZB PMVLZB PMVNZB PMVZB PSUBSIW

Table 8.1 - Extended MMX Instructions

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Generated on Sat Aug 8 10:13:00 2009