BCOS Transition State 2 Specification

BCOS Transition State 2 Specification
Version 1.0
(Preliminary Draft)

Contents

1                Overview
2                CPUs
2.1                BSP CPU
2.2                AP CPU
3                Kernel Setup Module
4                Hardware And Firmware
4.1                A20 Gate
4.2                Other Hardware
5                Boot Catalogue

Tables

Table 2.1      General Registers And Segment Registers
Table 2.2      EFLAGS
Table 2.3      Control Registers And Miscellaneous Registers
Table 2.4      CR0 Control Register
Table 2.5      General Registers And Segment Registers
Table 5.1      Required Boot Catalogue Entries
Table 5.2      Optional Boot Catalogue Entries

1   Overview

There's several stages used during boot, and several specifications that describe the state the computer must be in before moving from one stage to another. This specification describes what state the computer must be in when the OS's Stage 2 Manager transfers control to a Kernel Setup Module (Stage 3).

It is possible for the Kernel Setup Module to encounter some sort of error condition before it has been able to talk to any Boot Output Modules. This is the only case that the Kernel Setup Module may return to the Stage 2 Manager. The Kernel Setup Module must leave the Stage 2 Manager in a functioning state until it is able to talk to Boot Output Modules.

2   CPUs

The Stage 2 Manager is responsible for starting AP CPUs.

2.1   BSP CPU

The BSP shall be in 32-bit protected mode. The contents of the CPU's general registers and segment registers must be as defined in Table 2.1: General Registers And Segment Registers.

Register

Contents

EAX

0x00000000 (to indicate that this CPU is the BSP)

EBX

Reserved (zero)

ECX

Reserved (zero)

EDX

Reserved (zero)

ESI

Physical address of the Boot Catalogue (see Chapter 5: Boot Catalogue)

EDI

Kernel Setup Module code base address

EBP

Reserved (zero)

ESP

Left pointing to the Stage 2 Manager's stack (to allow the Kernel Setup Module to return)

Set to 32-bit, "read/execute", CPL=0, limit = 0xFFFFFFFF, base = Kernel Setup Module base address

EIP

Obtained from the Kernel Setup Module's executable header

Set to 32-bit, "read/write", limit = 0xFFFFFFFF, base = Kernel Setup Module code base address

Set to 32-bit, "read/write", limit = 0xFFFFFFFF, base = 0x00000000

Left pointing to the Stage 2 Manager's stack (to allow the Kernel Setup Module to return)

EFLAGS

See Table 2.2: EFLAGS

Table 2.1 - General Registers And Segment Registers

Bit/s

State

0 to 7

Undefined

8 (TF)

Clear (single-stepping disabled)

9 (IF)

Clear (interrupts disabled)

10 to 16

Undefined

17 (VM)

Clear (Virtual-8086 Mode disabled)

18 (AC)

Clear (Alignment Check disabled)

19 to 31

Undefined

Table 2.2 - EFLAGS

The BSP's control registers and miscellaneous registers must be as defined in Table 2.3: Control Registers And Miscellaneous Registers.

Register

Contents

CR0

See Table 2.4: CR0 Control Register

CR1 (if present)

Undefined

CR2

Undefined

CR3

Undefined

CR4 (if present)

All bits clear

IDTR

Left pointing to the Stage 2 Manager's IDT

GDTR

Left pointing to the Stage 2 Manager's GDT

LDTR

Undefined

Table 2.3 - Control Registers And Miscellaneous Registers

Bit/s

State

0 (PE)

Set (protected mode enabled)

1 (MP)

Undefined

2 (EM)

Undefined

3 (TS)

Undefined

4 (ET)

Undefined

5 (NE)

Undefined

6 to 15

Undefined

16 (WP)

Undefined

18 (AM)

Undefined

19 to 28

Undefined

29 (NW)

Same state as firmware left it

30 (CD)

Same state as firmware left it

31 (PG)

Undefined

Table 2.4 - CR0 Control Register

All MSRs must be left in the state that the firmware left them in, excluding MSRs changed during CPU detection.

All FPU, MMX and SSE registers (if present) are in an undefined state; including the FPU Control Register, the FPU Status Register, the FPU Tag Register, the FPU Last Instruction Pointer register, the FPU Last Data Pointer register, the FPU Operand register and the MXCSR Register.

2.2 AP CPU

In general, the AP CPUs must be in the same state as the BSP CPU, except for the general registers and segment registers. The contents of the AP CPU's general registers and segment registers must be as defined in Table 2.5: General Registers And Segment Registers.

Register

Contents

EAX

0x00000001 (to indicate that this CPU is an AP)

EBX

Reserved (zero)

ECX

Reserved (zero)

EDX

Reserved (zero)

ESI

Reserved (zero)

EDI

Reserved (zero)

EBP

Reserved (zero)

ESP

Left pointing to the AP CPU's stack

Set to 32-bit, "read/execute", CPL=0, limit = 0xFFFFFFFF, base = Kernel Setup Module base address

EIP

Obtained from the Kernel Setup Module's executable header

Set to 32-bit, "read/write", limit = 0xFFFFFFFF, base = Kernel Setup Module code base address

Set to 32-bit, "read/write", limit = 0xFFFFFFFF, base = 0x00000000

Left pointing to the AP CPU's stack

EFLAGS

See Table 2.2: EFLAGS

Table 2.5 - General Registers And Segment Registers

AP CPUs must not attempt to return to the Stage 2 Manager.

3   Kernel Setup Module

The Kernel Setup Module must be loaded into physically contiguous pages of RAM. To do this the previous stage allocates enough pages to contain the Kernel Setup Module plus any pages that the Kernel Setup Module needs for uninitialized data (as determined by the "Offset for the end of the uninitialized data area" field in the Platform Header - see BCOS Native Executable File Format Specification, Section 4.4: Uninitialized Area for more information).

Normally, executable files are loaded at address 0x00001000 in the address space. To emulate this (and allow for the Kernel Setup Module to be created using the standard executable file format), the "Kernel Setup Module code base address" (which is used for CS, DS, ES and SS segment base addresses) must be 4096 bytes less than the physical address of the Kernel Setup Module. The page at the "Kernel Setup Module base address" shouldn't be allocated as part of the physically contiguous pages of RAM that were allocated for the Kernel Setup Module.

4   Hardware And Firmware

4.1   A20 Gate

For normal operation the A20 gate should be enabled (so that the operating system can access every second MiB of the physical address space); however, a boot loader may deliberately disable the A20 gate for testing purposes, and if the boot loader is unable to enable or disable the A20 gate it must still continue to boot.

The boot loader must correctly report the state of the A20 gate in the Boot Catalogue (even if the boot loader is unable to enable/disable the A20 gate).

4.2   Other Hardware

All other hardware, including interrupt controllers (e.g. the PIC chips), timers, etc; remain in an undefined state.

5   Boot Catalogue

A valid Boot Catalogue must exist, and must include all of the entries listed in Table 5.1: Required Boot Catalogue Entries. Additional entries listed in Table 5.2: Optional Boot Catalogue Entries are optional, but recommended where possible.

BCOS Boot Catalogue Specification, Section 3.1: Type 0x00000001 - Boot Loader Identification Entry

BCOS Boot Catalogue Specification, Section 3.2: Type 0x00000003 - Trusted Area Entry

BCOS Boot Catalogue Specification, Section 3.7: Type 0x80000001 - Faulty RAM List Entry

BCOS Boot Catalogue Specification, Section 3.8: Type 0x80000002 - Physical Address Space Map Entry

BCOS Boot Catalogue Specification, Section 3.9: Type 0x80000003 - Faulty Page Bitmap Entry

BCOS Boot Catalogue Specification, Section 3.10: Type 0x80000004 - Free Page Bitmap Entry

BCOS Boot Catalogue Specification, Section 3.11: Type 0x80000005 - Boot Script Entry

BCOS Boot Catalogue Specification, Section 3.12: Type 0x80000006 - Boot Image Entry

BCOS Boot Catalogue Specification, Section 3.13: Type 0x80000007 - Boot Log Entry

BCOS Boot Catalogue Specification, Section 3.16: Type 0x80000022 - Boot Script Workspace Entry

Table 5.1 - Required Boot Catalogue Entries

Note that a Trusted Area Entry is required for each area of RAM that must work correctly for the computer to boot reliably.