Common PC BIOS Module Transition State Specification

Common PC BIOS Module Transition State Specification
Version 1.0
(Preliminary Draft)

Contents

1                Overview
2                CPUs
2.1                BSP
3                Hardware And PC BIOS
3.1                A20 Gate
4                Boot Catalogue
5                Common PC BIOS Module
5.1                Common PC BIOS Module Entry Point

Tables

Table 2.1      General Registers And Segment Registers
Table 2.2      Boot Flags
Table 2.3      EFLAGS
Table 2.4      Control Registers And Miscellaneous Registers
Table 2.5      CR0 Control Register
Table 4.1      Required Boot Catalogue Entries

1   Overview

There's several stages used during boot, and several specifications that describe the state the computer must be in before moving from one stage to another. For example, the BCOS Transition State 1 Specification describes what state the computer must be in before the OS's Boot Manager (the first "boot loader independant" stage) is started.

Some boot loaders are designed to go from the state the computer was in (e.g. the state the firmware left the computer in) directly to Transition State 1. However, for the PC BIOS there's several boot loaders, where the main difference between these boot loaders is how they obtain the additional files needed for boot (e.g. loaded from floppy disk, downloaded from a TFTP server, etc). Therefore, to make code maintenance easier these boot loaders are split in half, where the first half (the boot loader itself) does some initial work (including downloading the additional files needed for boot) and the second half (the Common PC BIOS Module) does the rest of the work needed to comply with the BCOS Transition State 1 Specification.

This specification describes the state that the computer must be in when the boot loader passes control to the Common PC BIOS Module.

2   CPUs

At boot, one CPU is classified as the BSP (Bootstrap Processor) and any additional CPUs are classified as APs (Application Processors), where all APs are left in a halted state by the BIOS and only the BSP is running. All APs need to remain in this halted state.

2.1   BSP

The BSP shall remain in real mode (where segment limits are all 64 KiB) or "unreal mode" (real mode, where some segment limits are larger than 64 KiB). The contents of the CPU's general registers and segment registers must be as defined in Table 2.1: General Registers And Segment Registers.

Register

Contents

EAX

Boot Flags (see Table 2.2: Boot Flags)

EBX

Reserved (zero)

ECX

Reserved (zero)

EDX

Reserved (zero)

ESI

Address of the Boot Catalogue (see Chapter 4: Boot Catalogue)

EDI

Reserved (zero)

EBP

Reserved (zero)

ESP

Undefined (may contain any value)

See Section 5.1: Common PC BIOS Module Entry Point

EIP

See Section 5.1: Common PC BIOS Module Entry Point

Undefined (may contain any value)

EFLAGS

See Table 2.3: EFLAGS

Table 2.1 - General Registers And Segment Registers

Bit/s

Description

Headless flag (set if video BIOS functions present, clear if video BIOS functions not present)

1 to 31

Reserved (clear)

Table 2.2 - Boot Flags

Bit/s

State

0 to 7

Undefined

8 (TF)

Clear (single-stepping disabled)

9 (IF)

Clear (interrupts disabled)

10 to 16

Undefined

17 (VM)

Clear (Virtual-8086 Mode disabled)

18 (AC)

Clear (Alignment Check disabled)

19 to 31

Undefined

Table 2.3 - EFLAGS

The BSP's control registers and miscellaneous registers must be as defined in Table 2.4: Control Registers And Miscellaneous Registers.

Register

Contents

CR0

See Table 2.5: CR0 Control Register

CR1 (if present)

Undefined

CR2

Undefined

CR3

Undefined

CR4 (if present)

All bits clear

IDTR

Same state as PC BIOS left it

GDTR

Undefined

LDTR

Undefined

Table 2.4 - Control Registers And Miscellaneous Registers

Bit/s

State

0 (PE)

Clear (protected mode disabled)

1 (MP)

Undefined

2 (EM)

Undefined

3 (TS)

Undefined

4 (ET)

Undefined

5 (NE)

Undefined

6 to 15

Undefined

16 (WP)

Undefined

18 (AM)

Undefined

19 to 28

Undefined

29 (NW)

Same state as PC BIOS left it

30 (CD)

Same state as PC BIOS left it

31 (PG)

Undefined

Table 2.5 - CR0 Control Register

All MSRs must be left in the state that the PC BIOS left them in.

All FPU, MMX and SSE registers (if present) are in an undefined state; including the FPU Control Register, the FPU Status Register, the FPU Tag Register, the FPU Last Instruction Pointer register, the FPU Last Data Pointer register, the FPU Operand register and the MXCSR Register.

3   Hardware And PC BIOS

The PC BIOS must be left in a functional state, including any devices it relies on, any areas of RAM it uses (BIOS Data Area, Extended BIOS Data Area, ACPI NVS Areas), and any areas of RAM it has left for the operating system (ACPI Reclaimable areas).

3.1   A20 Gate

For normal operation the A20 gate should be enabled (so that the operating system can access every second MiB of the physical address space); however, a boot loader may deliberately disable the A20 gate for testing purposes, and if the boot loader is unable to enable or disable the A20 gate it must still continue to boot.

The boot loader must correctly report the state of the A20 gate in the Boot Catalogue (even if the boot loader is unable to enable/disable the A20 gate).

4   Boot Catalogue

A valid Boot Catalogue must exist, and must include all of the entries listed in Table 4.1: Required Boot Catalogue Entries. The Boot Catalogue must not include any entries that are not listed in Table 4.1: Required Boot Catalogue Entries.

BCOS Boot Catalogue Specification, Section 3.1: Type 0x00000001 - Boot Loader Identification Entry

BCOS Boot Catalogue Specification, Section 3.2: Type 0x00000003 - Trusted Area Entry

BCOS Boot Catalogue Specification, Section 3.7: Type 0x80000001 - Faulty RAM List Entry

BCOS Boot Catalogue Specification, Section 3.8: Type 0x80000002 - Physical Address Space Map Entry

BCOS Boot Catalogue Specification, Section 3.9: Type 0x80000003 - Faulty Page Bitmap Entry

BCOS Boot Catalogue Specification, Section 3.10: Type 0x80000004 - Free Page Bitmap Entry

BCOS Boot Catalogue Specification, Section 3.11: Type 0x80000005 - Boot Script Entry

BCOS Boot Catalogue Specification, Section 3.12: Type 0x80000006 - Boot Image Entry

BCOS Boot Catalogue Specification, Section 3.13: Type 0x80000007 - Boot Log Entry

Table 4.1 - Required Boot Catalogue Entries

Note that a Trusted Area Entry is required for each area of RAM that must work correctly for the computer to boot reliably.

5 Common PC BIOS Module

The Common PC BIOS Module must exist in a 60 KiB area of RAM that was allocated using the Free Page Bitmap in the Boot Catalogue. This area of RAM must be entirely addressable with real mode addressing.

The Common PC BIOS uses the last 60 KiB of a 64 KiB area, where the first 4 KiB is unused/untouched and doesn't need to be allocated (and doesn't even need to be RAM). This implies that the highest possible location for the 60 KiB area of RAM allocated for the Common PC BIOS is from 0x00100000 to 0x0010EFFF; and the lowest possible location for the 60 KiB area of RAM allocated for the Common PC BIOS is from 0x00001000 to 0x0000FFFF.

5.1 Common PC BIOS Module Entry Point

When passing control to the Common PC BIOS Module both CS and EIP must be set (e.g. via. an indirect far jump). The address of the entry point is calculated so that the code segment used by the Common PC BIOS Module begins at the address the Common PC BIOS Module was loaded minus 4 KiB. The offset within this code segment is taken from the Common PC BIOS Module's header and will always be greater than 0x00001000.

For example, if RAM is allocated for the Common PC BIOS from 0x00100000 to 0x0010EFFF then CS would equal "(0x00100000 - 0x00001000) >> 4" or 0xFF00, and if the entry point (from the Common PC BIOS Module's header) is 0x1234 then CS:EIP for the entry point would be 0xFF00:0x1234.

Generated on Sat Oct 17 03:21:55 2009