80x86 CPU Description Structure Include File

80x86 CPU Description Structure Include File
File: 80x86/inc/kernel/cpu.inc

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CPU Structures And Definitions

CPU Data Structure

The following structure contains static fields that describe a CPU type. The same data may be used to describe one or more CPUs.

14: struc CPUdescStruct
15:
16: ;General Information
17:
18:       .flags:                       resd 1                        ;CPU description flags
19:       .CPUIDcloakType:              resd 1                        ;Method to use to cloak/uncloak CPUID
20:
21: ;CPU Identification
22:
23:       .vendorID:                    resd 1                        ;Vendor ID
24:
25:       .vendorString:                resb 12                       ;CPU vendor string
26:                                     resb 1                        ;Used for ASCIIZ termination
27:                                     alignb 4
28:       .brandString:                 resb 64                       ;CPU brand string
29:                                     resb 1                        ;Used for ASCIIZ termination
30:                                     alignb 4
31:
32:       .family:                      resd 1                        ;CPU family
33:       .model:                       resb 1                        ;CPU model number
34:       .stepping:                    resb 1                        ;CPU stepping
35:       .revision:                    resb 1                        ;CPU revision
36:                                     alignb 4
37:       .softRevision:                resq 2                        ;Software revision (e.g. microcode)
38:       .platformID:                  resd 1                        ;CPU platform ID
39:                                     alignb 4
40:       .physAddressBits:             resb 1                        ;Number of physical address bits
41:       .linearAddressBits:           resb 1                        ;Number of linear address bits
42:                                     alignb 4
43:
44: ;CPU Features
45:
46:       .userFeatures:                resq 2                        ;User-mode features flags
47:       .kernelFeatures:              resq 2                        ;Kernel-mode features flags
48:       .powerManagementFeatures:     resd 1                        ;Power management features (depends on CPU vendor)
49:
50: ;CPU bugs
51:
52:       .errata:                      resq 2                        ;Errata flags
53:       .flaws:                       resq 2                        ;Flaws flags
54:
55: ;CPU Internal Caches
56:
57:       .CLFLUSHlineSize:             resd 1                        ;CLFLUSH cache line size in bytes (0 if unknown or CLFLUSH not supported)
58:       .MONITORsmallest:             resd 1                        ;Smallest monitor line size in bytes
59:       .MONITORlargest:              resd 1                        ;Largest monitor line size in bytes
60:
61:       .cacheFlags:                  resd 1                        ;Cache flags
62:
63:       .L1cacheData:
64:       .L1cacheSize:                 resd 1                        ;L1 cache size (instruction or unified)
65:       .L1cacheAssoc:                resd 1                        ;L1 cache associativity (instruction or unified)
66:       .L1dataCacheSize:             resd 1                        ;L1 data cache size (if not unified)
67:       .L1dataCacheAssoc:            resd 1                        ;L1 data cache associativity (if not unified)
68:       .L1sharedCPUs:                resd 1                        ;Number of APIC IDs served by L1 caches - 1
69:
70:       .L2cacheData:
71:       .L2cacheSize:                 resd 1                        ;L2 cache size (instruction or unified)
72:       .L2cacheAssoc:                resd 1                        ;L2 cache associativity (instruction or unified)
73:       .L2dataCacheSize:             resd 1                        ;L2 data cache size (if not unified)
74:       .L2dataCacheAssoc:            resd 1                        ;L2 data cache associativity (if not unified)
75:       .L2sharedCPUs:                resd 1                        ;Number of APIC IDs served by L2 caches - 1
76:
77:       .L3cacheData:
78:       .L3cacheSize:                 resd 1                        ;L3 cache size (instruction or unified)
79:       .L3cacheAssoc:                resd 1                        ;L3 cache associativity (instruction or unified)
80:       .L3dataCacheSize:             resd 1                        ;L3 data cache size (if not unified)
81:       .L3dataCacheAssoc:            resd 1                        ;L3 data cache associativity (if not unified)
82:       .L3sharedCPUs:                resd 1                        ;Number of APIC IDs served by L3 caches - 1
83:
84: ;CPU Internal Topology
85:
86:       .APICID_packageShift:         resd 1                        ;Number of times to shift APIC ID right to get package number
87:       .APICID_coreShift:            resd 1                        ;Number of times to shift APIC ID right to get global core ID
88:       .APICID_coreMask:             resd 1                        ;Mask to find core number within package from global core ID
89:       .APICID_CPUshift:             resd 1                        ;Number of times to shift APIC ID right to get logical CPU ID
90:       .APICID_CPUmask:              resd 1                        ;Mask to find logical CPU number within core from APIC ID
91:
92:                                     alignb 4                      ;Structure must be a multiple of 4 bytes
93: endstruc

CPU Description Flags

99: %define CPUFLAG_hasModelInfo                    0x00000001        ;Set if the model and stepping information is known
100: %define CPUFLAG_hasRevisionInfo                 0x00000002        ;Set if the revision is known
101: %define CPUFLAG_hasIntelSoftRevision            0x00000004        ;Set if the software revision is known and is in Intel format
102: %define CPUFLAG_hasTransSoftRevision            0x00000008        ;Set if the software revision is known and is in Transmeta format
103: %define CPUFLAG_hasPlatformID                   0x00000010        ;Set if the platform ID is known

CPUID Cloaking Type

109: %define CPUCLOAK_none 0x00000000 ;No cloaking, or non-reversible cloaking
110: %define CPUCLOAK_Intel 0x00000000 ;Intel cloaking (CPUID limited to max. function 0x00000003)

CPU Vendor ID

116: %define CPUVENDOR_unknown                       0x00000000        ;Unknown CPU vendor
117: %define CPUVENDOR_AMD                           0x00000001
118: %define CPUVENDOR_IBM                           0x00000002
119: %define CPUVENDOR_Intel                         0x00000003
120: %define CPUVENDOR_Centaur                       0x00000004
121: %define CPUVENDOR_Cyrix                         0x00000005
122: %define CPUVENDOR_NSC                           0x00000006
123: %define CPUVENDOR_Rise                          0x00000007
124: %define CPUVENDOR_SiS                           0x00000008
125: %define CPUVENDOR_Transmeta                     0x00000009
126: %define CPUVENDOR_UMC                           0x0000000A
127: %define CPUVENDOR_VIA                           0x0000000B

CPU User Feature Flags

These feature flags are defined in a separate include file.

CPU Kernel Feature Flags

These feature flags are defined in a separate include file.

CPU Errata Flags

145: %define CPU_ERRATA_noCR4 0 ;This flag is set if the CPU doesn't support CR4

CPU Power Management Flags

151: ;Flags for Transmeta
152:
153: %define CPU_PM_TMA_LongRun                      1                 ;Transmeta LongRun
154: %define CPU_PM_TMA_LongRunTI                    3                 ;Transmeta LongRun Table Interface
155: %define CPU_PM_TMA_PBE                          12                ;Transmeta Processor Break Events

CPU Flaw Flags

161: %define CPU_FLAW_UNKNOWN 0 ;This flag is always set for CPUs that don't have known errata

CPU Cache Flags

167: %define CPUCACHEFLG_L1known                     0x00000001
168: %define CPUCACHEFLG_L1unified                   0x00000002
169: %define CPUCACHEFLG_L1trace                     0x00000004
170:
171: %define CPUCACHEFLG_L2known                     0x00000100
172: %define CPUCACHEFLG_L2unified                   0x00000200
173: %define CPUCACHEFLG_L2exclusive                 0x00000400
174: %define CPUCACHEFLG_L2victim                    0x00000800
175:
176: %define CPUCACHEFLG_L3known                     0x00010000
177: %define CPUCACHEFLG_L3unified                   0x00020000
178: %define CPUCACHEFLG_L3exclusive                 0x00040000
179: %define CPUCACHEFLG_L3victim                    0x00080000

Generated on Fri Oct 30 20:55:42 2009